[coreboot-gerrit] Change in ...coreboot[master]: coreboot: add post code for invalid FSP

[Keith Short (Code Review)]

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32772

Change subject: coreboot: add post code for invalid FSP
......................................................................

coreboot: add post code for invalid FSP

Add a new post code POST_INVALID_FSP, used when coreboot fails to locate
or validate Intel FSP.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short 
---
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/include/console/post_codes.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
5 files changed, 19 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32772/1

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index b3afb98..879b477 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -276,8 +276,10 @@

upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);

-	if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
+	if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) {
+		post_code(POST_INVALID_FSP);
    	die("Invalid FSPM signature!\n");
+	}

/* Copy the default values from the UPD area */
    memcpy(&fspm_upd, upd, sizeof(fspm_upd));
@@ -289,8 +291,10 @@

/* Fill common settings on behalf of chipset. */
    if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
-					memmap) != CB_SUCCESS)
+					memmap) != CB_SUCCESS) {
+		post_code(POST_INVALID_FSP);
    	die("FSPM_ARCH_UPD not found!\n");
+	}

/* Give SoC and mainboard a chance to update the UPD */
    platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 402b05d..dd4d730 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -32,8 +32,10 @@

supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);

-	if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
+	if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) {
+		post_code(POST_INVALID_FSP);
    	die("Invalid FSPS signature\n");
+	}

upd = xmalloc(sizeof(FSPS_UPD));

diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 637083a..ce26aac 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -333,6 +333,14 @@
 #define POST_INVALID_CBFS			0xE1

/**
+ * \brief FSP error
+ *
+ * Set if firmware failed to find or validate a FSP resource, or another
+ * FSP error occurred.
+ */
+#define POST_INVALID_FSP			0xE2
+
+/**
  * \brief TPM failure
  *
  * An error with the TPM, either unexepcted state or communications failure.
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index c46b09e..93900ef 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -208,6 +208,7 @@
    post_code(0x48);
    printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
    fsp_early_init(fsp_info_header);
+	post_code(POST_INVALID_FSP);
    die("Uh Oh! fsp_early_init should not return here.\n");
 }

diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index a75dabd..12a1702 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -84,6 +84,7 @@
    post_code(0x48);
    printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
    fsp_early_init(fsp_info_header);
+	post_code(POST_FSP_FAILURE);
    die("Uh Oh! fsp_early_init should not return here.\n");
 }