Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43094 )
Change subject: nb/intel/haswell: Add `mb_post_raminit_setup` function ......................................................................
nb/intel/haswell: Add `mb_post_raminit_setup` function
This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything.
Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c 3 files changed, 24 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/43094/1
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index ea1193f..5ddbd03 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -26,8 +26,24 @@ RCBA_END_CONFIG, };
-void mainboard_config_superio(void) +void mb_post_raminit_setup(void) { + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } }
void mainboard_romstage_entry(void) @@ -86,21 +102,4 @@ };
romstage_common(&romstage_params); - - u8 enable_peg; - if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) - enable_peg = 0; - - bool power_en = pmh7_dgpu_power_state(); - - if (enable_peg != power_en) - pmh7_dgpu_power_enable(!power_en); - - if (!enable_peg) { - // Hide disabled dGPU device - u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~DEVEN_D1F0EN; - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); - } } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b98d880..0b35acb 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -198,6 +198,7 @@ void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); +void mb_post_raminit_setup(void); /* optional */
void haswell_early_initialization(void); void haswell_late_initialization(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 579eca7..e5e29c1 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h>
+void __weak mb_post_raminit_setup(void) +{ +} + void romstage_common(const struct romstage_params *params) { int wake_from_s3; @@ -77,5 +81,7 @@
romstage_handoff_init(wake_from_s3);
+ mb_post_raminit_setup(); + post_code(0x3f); }