[coreboot-gerrit] [XL] Change in coreboot[main]: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC

[Paul Menzel (Code Review)]

Attention is currently required from: Jérémy Compostella, Shuo Liu, [e-mail].

Paul Menzel has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )

Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
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Patch Set 4:

(1 comment)

File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:

https://review.coreboot.org/c/coreboot/+/83192/comment/c52920c1_3f887865?usp... :
PS4, Line 100: This structure holds the DLL configuration
             :   register values that will be programmed by RC.
             :   Those policies should be used by platform if default values
             :   provided by RC are not sufficient to provide stable operation
             :   at all supported speed modes. RC will blindly set the DLL values
             :   as provided in this structure.
Line breaks make it harder to read.