Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61772 )
Change subject: libpayload: Add support for PCI MMIO CONFIG access. ......................................................................
libpayload: Add support for PCI MMIO CONFIG access.
Add MMIO method to access PCIe config space from payloads. Defined read/write config 8/16/32 functions for ARM arch in libpayload pci driver. In pci driver, PCIe MMIO config base info extracts through coreboot tables and initializes the ATU for every read/write config access.
Change-Id: Id6ebda0b49b8204996bb86e769a9fc29644d5f01 Signed-off-by: Prasad Malisetty quic_pmaliset@quicinc.com --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc R payloads/libpayload/drivers/pci_io_ops.c C payloads/libpayload/drivers/pci_mmio_ops.c A payloads/libpayload/drivers/qc_pci_mmio_ops.c M payloads/libpayload/include/pci.h A payloads/libpayload/include/qc_pci.h 8 files changed, 252 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/61772/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 4f8896a..4c2031d 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -277,6 +277,21 @@ depends on SERIAL_CONSOLE default n
+config PCI + bool "PCI driver" + depends on SERIAL_CONSOLE + default n + +config MMCONF_SUPPORT + bool "MMCONF support for drivers" + depends on SERIAL_CONSOLE + default n + +config QC_MMCONF_SUPPORT + bool "QC MMCONF support for drivers" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE @@ -402,11 +417,6 @@
menu "Drivers"
-config PCI - bool "Support for PCI devices" - depends on ARCH_X86 # for now - default y - config NVRAM bool "Support for reading/writing NVRAM bytes" depends on ARCH_X86 # for now diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine index 18ca19d..157a5c7 100644 --- a/payloads/libpayload/configs/config.herobrine +++ b/payloads/libpayload/configs/config.herobrine @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y +CONFIG_LP_PCI=y +CONFIG_LP_MMCONF_SUPPORT=y +CONFIG_LP_QC_MMCONF_SUPPORT=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 41fda5b..fac3bdf 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -28,7 +28,17 @@ ## SUCH DAMAGE. ##
-libc-$(CONFIG_LP_PCI) += pci.c +# only do the below if CONFIG_LP_PCI +ifeq ($(CONFIG_LP_PCI),y) + +ifeq ($(CONFIG_LP_MMCONF_SUPPORT),y) +libc-$(CONFIG_LP_MMCONF_SUPPORT) += pci_mmio_ops.c +libc-$(CONFIG_LP_QC_MMCONF_SUPPORT) += qc_pci_mmio_ops.c +else +libc-$(CONFIG_LP_PCI) += pci_io_ops.c +endif + +endif
libc-$(CONFIG_LP_SPEAKER) += speaker.c
diff --git a/payloads/libpayload/drivers/pci.c b/payloads/libpayload/drivers/pci_io_ops.c similarity index 97% rename from payloads/libpayload/drivers/pci.c rename to payloads/libpayload/drivers/pci_io_ops.c index 90e9220..7031f34 100644 --- a/payloads/libpayload/drivers/pci.c +++ b/payloads/libpayload/drivers/pci_io_ops.c @@ -67,51 +67,42 @@ }
static int find_on_bus(int bus, unsigned short vid, unsigned short did, - pcidev_t * dev) + pcidev_t *dev) { int devfn; u32 val; unsigned char hdr; - for (devfn = 0; devfn < 0x100; devfn++) { int func = devfn & 0x7; int slot = (devfn >> 3) & 0x1f; - val = pci_read_config32(PCI_DEV(bus, slot, func), REG_VENDOR_ID); - if (val == 0xffffffff || val == 0x00000000 || val == 0x0000ffff || val == 0xffff0000) continue; - if (val == ((did << 16) | vid)) { *dev = PCI_DEV(bus, slot, func); return 1; } - hdr = pci_read_config8(PCI_DEV(bus, slot, func), REG_HEADER_TYPE); hdr &= 0x7F; - if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { unsigned int busses; busses = pci_read_config32(PCI_DEV(bus, slot, func), REG_PRIMARY_BUS); busses = (busses >> 8) & 0xFF; - /* Avoid recursion if the new bus is the same as * the old bus (insert lame The Who joke here) */ - if ((busses != bus) && find_on_bus(busses, vid, did, dev)) return 1; } } - return 0; }
-int pci_find_device(u16 vid, u16 did, pcidev_t * dev) +int pci_find_device(u16 vid, u16 did, pcidev_t *dev) { return find_on_bus(0, vid, did, dev); } diff --git a/payloads/libpayload/drivers/pci.c b/payloads/libpayload/drivers/pci_mmio_ops.c similarity index 71% copy from payloads/libpayload/drivers/pci.c copy to payloads/libpayload/drivers/pci_mmio_ops.c index 90e9220..fd72a71 100644 --- a/payloads/libpayload/drivers/pci.c +++ b/payloads/libpayload/drivers/pci_mmio_ops.c @@ -1,9 +1,7 @@ /* + *Copyright (C) 2021 Qualcomm Technologies, Inc. * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008 coresystems GmbH - * - * Redistribution and use in source and binary forms, with or without + *Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright @@ -25,93 +23,90 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - */ +*/
#include <libpayload.h> #include <pci.h>
-u8 pci_read_config8(pcidev_t device, u16 reg) +u8 pci_read_config8(pcidev_t dev, u16 reg) { - outl(device | (reg & ~3), 0xCF8); - return inb(0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + return read8((void *)(cfg_address | reg)); }
-u16 pci_read_config16(pcidev_t device, u16 reg) +u16 pci_read_config16(pcidev_t dev, u16 reg) { - outl(device | (reg & ~3), 0xCF8); - return inw(0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + return read16((void *)(cfg_address | (reg & ~1))); }
-u32 pci_read_config32(pcidev_t device, u16 reg) +u32 pci_read_config32(pcidev_t dev, u16 reg) { - outl(device | (reg & ~3), 0xCF8); - return inl(0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + return read32((void *)(cfg_address | (reg & ~3))); }
-void pci_write_config8(pcidev_t device, u16 reg, u8 val) +void pci_write_config8(pcidev_t dev, u16 reg, u8 val) { - outl(device | (reg & ~3), 0xCF8); - outb(val, 0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + write8((void *)(cfg_address | reg), val); }
-void pci_write_config16(pcidev_t device, u16 reg, u16 val) +void pci_write_config16(pcidev_t dev, u16 reg, u16 val) { - outl(device | (reg & ~3), 0xCF8); - outw(val, 0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + write16((void *)(cfg_address | (reg & ~1)), val); }
-void pci_write_config32(pcidev_t device, u16 reg, u32 val) +void pci_write_config32(pcidev_t dev, u16 reg, u32 val) { - outl(device | (reg & ~3), 0xCF8); - outl(val, 0xCFC + (reg & 3)); + uintptr_t cfg_address = get_pci_mmio_cfgbase(dev); + + write32((void *)(cfg_address | (reg & ~3)), val); }
static int find_on_bus(int bus, unsigned short vid, unsigned short did, - pcidev_t * dev) + pcidev_t *dev) { int devfn; u32 val; unsigned char hdr; - for (devfn = 0; devfn < 0x100; devfn++) { int func = devfn & 0x7; int slot = (devfn >> 3) & 0x1f; - val = pci_read_config32(PCI_DEV(bus, slot, func), REG_VENDOR_ID); - if (val == 0xffffffff || val == 0x00000000 || val == 0x0000ffff || val == 0xffff0000) continue; - if (val == ((did << 16) | vid)) { *dev = PCI_DEV(bus, slot, func); return 1; } - hdr = pci_read_config8(PCI_DEV(bus, slot, func), REG_HEADER_TYPE); hdr &= 0x7F; - if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { unsigned int busses; busses = pci_read_config32(PCI_DEV(bus, slot, func), REG_PRIMARY_BUS); busses = (busses >> 8) & 0xFF; - /* Avoid recursion if the new bus is the same as * the old bus (insert lame The Who joke here) */ - if ((busses != bus) && find_on_bus(busses, vid, did, dev)) return 1; } } - return 0; }
-int pci_find_device(u16 vid, u16 did, pcidev_t * dev) +int pci_find_device(u16 vid, u16 did, pcidev_t *dev) { return find_on_bus(0, vid, did, dev); } diff --git a/payloads/libpayload/drivers/qc_pci_mmio_ops.c b/payloads/libpayload/drivers/qc_pci_mmio_ops.c new file mode 100644 index 0000000..2ba2fa9 --- /dev/null +++ b/payloads/libpayload/drivers/qc_pci_mmio_ops.c @@ -0,0 +1,117 @@ +/* + *Copyright (C) 2021 Qualcomm Technologies, Inc. + * + *Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. +*/ + +#include <libpayload.h> +#include <pci.h> +#include <qc_pci.h> + +static void dw_pcie_writel_ob_unroll(void *atu_base, uint32_t index, + uint32_t reg, uint32_t val) +{ + uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + + write32(atu_base + offset + reg, val); +} + +static uint32_t dw_pcie_readl_ob_unroll(void *atu_base, uint32_t index, + uint32_t reg) +{ + uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + + return read32(atu_base + offset + reg); +} + +static void qcom_dw_pcie_prog_outbound_atu(void *pcie, int index, int type, + uint64_t cpu_addr, uint64_t pcie_addr, + uint32_t size) +{ + uint32_t retries, val; + + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pcie_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pcie_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { + val = dw_pcie_readl_ob_unroll(pcie, index, + PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return; + udelay(LINK_WAIT_IATU); + } + + printf("Outbound iATU is not being enabled\n"); +} + +/* Get PCI MMCONFIG BASE address */ +uintptr_t get_pci_mmio_cfgbase(pcidev_t dev) +{ + int atu_type, busdev; + uint32_t cfg_size; + void *cfg_address; + void *atu_base; + uint32_t current_bus = PCIE_BUS(dev); + uint32_t devfn = ((dev >> 3) & 0x1f) | (dev & 0x07); + struct pci_config_info *pci_mmio_info; + + busdev = PCIE_ATU_BUS(current_bus) | + PCIE_ATU_DEV(PCIE_SLOT(dev)) | + PCIE_ATU_FUNC(PCIE_FUNC(dev)); + + if (current_bus == 1) + /* For local bus, change TLP Type field to 4. */ + atu_type = PCIE_ATU_TYPE_CFG0; + else + /* Otherwise, change TLP Type field to 5. */ + atu_type = PCIE_ATU_TYPE_CFG1; + + /* Extract PCI config base, size and ATU base from coreboot */ + pci_mmio_info = (struct pci_config_info *) lib_sysinfo.pci_config_info; + cfg_address = (void*) pci_mmio_info->config_base; + cfg_size = (uint32_t) pci_mmio_info->config_size; + atu_base = (void *) pci_mmio_info->atu_base; + + qcom_dw_pcie_prog_outbound_atu(atu_base, PCIE_ATU_REGION_INDEX1, + atu_type, (uint64_t)cfg_address, + busdev, cfg_size); + + return (uintptr_t) cfg_address | devfn; +} + diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index ce5081c..8c34777 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -31,6 +31,8 @@ #define _PCI_H
#include <arch/types.h> +#include <stdint.h> + typedef u32 pcidev_t;
/* Device config space registers. */ @@ -100,6 +102,9 @@ #define PCI_SLOT(_d) ((_d >> 11) & 0x1f) #define PCI_FUNC(_d) ((_d >> 8) & 0x7)
+/*Platform specific function to get the config base address */ +uintptr_t get_pci_mmio_cfgbase(pcidev_t dev); + u8 pci_read_config8(u32 device, u16 reg); u16 pci_read_config16(u32 device, u16 reg); u32 pci_read_config32(u32 device, u16 reg); diff --git a/payloads/libpayload/include/qc_pci.h b/payloads/libpayload/include/qc_pci.h new file mode 100644 index 0000000..4a2a628 --- /dev/null +++ b/payloads/libpayload/include/qc_pci.h @@ -0,0 +1,70 @@ +/* + *Copyright (C) 2022 Qualcomm Technologies, Inc. + * + *Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. +*/ +#ifndef _QC_PCI_H +#define _QC_PCI_H + +/* + * iATU Unroll-specific register definitions + */ +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0C +#define PCIE_ATU_UNR_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_ENABLE (0x1 << 31) + +#define PCIE_FUNC(d) (((d) >> 8) & 0x7) +#define PCIE_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCIE_MASK_BUS(bdf) ((bdf) & 0xffff) +#define PCIE_BUS(d) (((d) >> 16) & 0xff) + +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C +#define LINK_WAIT_IATU 10000 +#define LINK_WAIT_MAX_IATU_RETRIES 5 + +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) + +#define lower_32_bits(n) ((u32)(n)) +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/* PCI MMIO info */ +struct pci_config_info { + uint64_t config_base; + uint64_t atu_base; + uint32_t config_size; +}; + +#endif