[coreboot-gerrit] [XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz

[Kiwi Liu (Code Review)]

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yidi Lin, Yu-Ping Wu.

Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84298?usp=email

to look at the new patch set (#13).

Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
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soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz

Mediatek SoCs start operating at eMMC clock around 2 MHz right after
power-on. In JEDEC spec, eMMC clock needs under 400 kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and the frequency
division value to 125. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set
the source clock frequency correctly, we can get the correct frequency
division value, and then get the correct clock output.

BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok

Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang 
Signed-off-by: Kiwi Liu 
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/13