HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6794
-gerrit
commit 4b17a101458ace96dc3e5a22a6ada91de1a2a78b Author: Elyes HAOUAS ehaouas@noos.fr Date: Thu Aug 28 19:42:29 2014 +0200
i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0
Change-Id: Ia0909866e2c8dd30b7f532ff184728bbdaf07b2f Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/intel/i945/early_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..603a89b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,10 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: /* 945G/945GZ/945GC/945P/945PL */ + printk(BIOS_DEBUG, "up to DDR2-667"); + break; + case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +198,7 @@ static void i945_setup_bars(void)
/* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +230,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 = 0x00000014; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +248,10 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; }
+ if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0;