Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email )
Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit ......................................................................
soc/intel/alderlake/tcss: Add definition of IOM_READY bit
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit before FSP Silicon Init to have USB functionality.
TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci.
Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/soc/intel/alderlake/include/soc/tcss.h 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83356/1
diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h index 014e307..825b6c7 100644 --- a/src/soc/intel/alderlake/include/soc/tcss.h +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -7,6 +7,10 @@ #define IOM_CSME_IMR_TBT_STATUS 0x14 #define TBT_VALID_AUTHENTICATION (1 << 30)
+/* TCSS IP status */ +#define IOM_TYPEC_STATUS_1 0x50 +#define IOM_READY (1 << 30) + /* IOM aux bias control registers in REGBAR MMIO space */ #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)