Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42440/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42440/3//COMMIT_MSG@9 PS3, Line 9: Add PchPmPwrCycDur to chip options to control the UPD : FSPS PchPmPwrCycDur from devicetree. The UPD determines the : minimum time a platform will stay in reset during host partition : reset with power cycle or global reset.
Please re-flow for 75 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... PS3, Line 319: * 4 = 4sec (default)
SI unit is *s*.
Ack
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... PS3, Line 321: uint8_t PchPmPwrCycDur;
`src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h` says that 0 is the default. […]
@Furquan, your comments are correct.