[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

[Arthur Heymans (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun.

Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email )

Change subject: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84085/comment/e47ec413_42023170?usp... :
PS1, Line 7: alderlake
> meteorlake

Done

https://review.coreboot.org/c/coreboot/+/84085/comment/d89b8c39_b8ab1ed9?usp... :
PS1, Line 15: bufferoverflow
> buffer overflow

Done