[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp: Add a workaround for multi socket xeon-sp

[Arthur Heymans (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu.

Hello Andrey Petrov, Christian Walter, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80579?usp=email

to look at the new patch set (#3).

Change subject: drivers/intel/fsp: Add a workaround for multi socket xeon-sp
......................................................................

drivers/intel/fsp: Add a workaround for multi socket xeon-sp

Starting with Intel CPX there is a bug in there reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the top of FSP heap is FspStackBase +
FspStackSize and the bottom is the bottom of CAR.

Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.

Signed-off-by: Arthur Heymans 
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
5 files changed, 33 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/3