John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
There are known limitation for D3Colde enabling on pre-QS platform. This change reads cpu id and disables TCSS D3Cold for pre-QS platform. For QS platform, D3Cold enabling will be based on mainboard configuration.
BUG=None TEST=Verified D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1) if platform TcssD3ColdeEnable is set to 1.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9..0c8344e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/lpss.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <security/vboot/vboot_common.h> @@ -85,6 +86,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + uint32_t cpu_id; FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev; @@ -114,7 +116,11 @@
/* D3Hot and D3Cold for TCSS */ params->D3HotEnable = config->TcssD3HotEnable; - params->D3ColdEnable = config->TcssD3ColdEnable; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) + params->D3ColdEnable = 0; + else + params->D3ColdEnable = config->TcssD3ColdEnable;
params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++)