[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail/lpss.c: Align with Braswell

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43195 )

Change subject: soc/intel/baytrail/lpss.c: Align with Braswell
......................................................................

soc/intel/baytrail/lpss.c: Align with Braswell

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/baytrail/lpss.c
1 file changed, 13 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index cdf78b7..08c3c05 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -15,16 +15,15 @@

#include "chip.h"

-static void dev_enable_acpi_mode(struct device *dev, int iosf_reg,
-				 int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 {
    struct reg_script ops[] = {
    	/* Disable PCI interrupt, enable Memory and Bus Master */
-		REG_PCI_OR16(PCI_COMMAND,
-			     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+		REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
    	/* Enable ACPI mode */
    	REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
    		    LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
+
    	REG_SCRIPT_END
    };
    struct resource *bar;
@@ -63,14 +62,17 @@
    reg_script_run_on_dev(dev, ops);
 }

+#define SET_IOSF_REG(name_) \
+	case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
+		do { \
+			*iosf_reg = LPSS_ ## name_ ## _CTL; \
+			*nvs_index = LPSS_NVS_ ## name_; \
+		} while (0)
+
 static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
 {
    *iosf_reg = -1;
    *nvs_index = -1;
-#define SET_IOSF_REG(name_) \
-	case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
-		*iosf_reg = LPSS_ ## name_ ## _CTL; \
-		*nvs_index = LPSS_NVS_ ## name_

switch (dev->path.pci.devfn) {
    SET_IOSF_REG(SIO_DMA1);
@@ -104,6 +106,8 @@
    }
 }

+#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
+
 static void i2c_disable_resets(struct device *dev)
 {
    /* Release the I2C devices from reset. */
@@ -112,9 +116,6 @@
    	REG_SCRIPT_END,
    };

-#define CASE_I2C(name_) \
-	case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
-
    switch (dev->path.pci.devfn) {
    CASE_I2C(I2C1):
    CASE_I2C(I2C2):
@@ -141,8 +142,7 @@
    if (iosf_reg < 0) {
    	int slot = PCI_SLOT(dev->path.pci.devfn);
    	int func = PCI_FUNC(dev->path.pci.devfn);
-		printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n",
-		       slot, func);
+		printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func);
    	return;
    }
    dev_enable_snoop_and_pm(dev, iosf_reg);