Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60181 )
Change subject: soc/intel/alderlake: Add minimal ACPI support for PEG ports ......................................................................
soc/intel/alderlake: Add minimal ACPI support for PEG ports
Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 --- M src/soc/intel/alderlake/acpi/pcie.asl M src/soc/intel/alderlake/chip.c 2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/60181/1
diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index a19feb7..f2123aa 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -299,3 +299,22 @@ Return (IRQM (RPPN)) } } + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) +Device (PEG0) +{ + Name (_ADR, 0x00060000) +} +#endif + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) +Device (PEG1) +{ + Name (_ADR, 0x00060002) +} + +Device (PEG2) +{ + Name (_ADR, 0x00010000) +} +#endif diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index ae28d18..1fa78fb 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -61,6 +61,9 @@
switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; + case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; + case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_IGD: return "GFX0"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC";