[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82431?usp=email )

Change subject: soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically
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Patch Set 14:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/82431/comment/dfafe098_ee33a61d?usp... :
PS12, Line 9: vtd_probe_bar_size is used to decide the BAR size.
> This is good idea, will check. […]

Hi Nico, Arthur,

This proves to work on SPR/GNR by reading PCI config space 0x180 of MMAP VTd devices (0x8086, 0x09a2).

While we have one open to discuss, besides Xeon-SP codes, the ACPI codes also needs to refer to the VTD bar size, e.g. 
https://review.coreboot.org/c/coreboot/+/82429.

For this we might have 2 solutions.

Solution #1 - to invoke https://review.coreboot.org/c/coreboot/+/82430 when CONFIG_SOC_INTEL_COMMON_BLOCK_VTD selected, and to return 4KiB otherwise.

Solution #2 - to define a weak function returning 4KiB but to override in Xeon-SP codes by checking MMAP VTd PCI config space 0x180.

Your opinion?