[coreboot-gerrit] Change in coreboot[master]: scpu/amd/{agesa,pi}/Kconfig: select SSE2

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37292 )

Change subject: scpu/amd/{agesa,pi}/Kconfig: select SSE2
......................................................................

scpu/amd/{agesa,pi}/Kconfig: select SSE2

SSE2 instructions are supported by family14 and newer.

SSE will be automatically enabled in bootblock_crt0 for platforms that
migrate to C bootblock. Because of that family specific CAR setup may
avoid additional code.

TEST=boot PC Engines apu1 and apu2

Signed-off-by: Michał Żygowski 
Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/pi/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37292/1

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index ddfe707..9956579 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -29,6 +29,7 @@
    select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
    select SMM_ASEG
    select NO_FIXED_XIP_ROM_SIZE
+	select SSE2

if CPU_AMD_AGESA

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index d18f873..728c7b1 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -28,6 +28,7 @@
    select SPI_FLASH if HAVE_ACPI_RESUME
    select SMM_ASEG
    select NO_FIXED_XIP_ROM_SIZE
+	select SSE2

if CPU_AMD_PI