Hello Aamir Bohra,
I'd like you to do a code review. Please visit
https://review.coreboot.org/20059
to review the following change.
Change subject: vendorcode/intel: Update FSP header files as per v48_20 ......................................................................
vendorcode/intel: Update FSP header files as per v48_20
Also add VariableNvsBufferPtr UPD.
Change-Id: I62b48bc1432e8d24baa1da4918a5b4b73b14597a Signed-off-by: Aamir Bohra aamir.bohra@intel.com Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 3 files changed, 92 insertions(+), 155 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/20059/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h index d1bb1fc..354dd8a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h @@ -37,11 +37,11 @@
#pragma pack(push, 1)
-#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554B4C47 /* 'GLKUPD_T' */
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B4C47 /* 'GLKUPD_M' */
-#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554B4C47 /* 'GLKUPD_S' */
#pragma pack(pop)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h index 2619171..6478f35 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -35,7 +35,7 @@
#include <FspUpd.h>
-#pragma pack(push, 1) +#pragma pack(1)
#define MAX_CHANNELS_NUM 4 @@ -157,25 +157,21 @@ UINT8 Package;
/** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 + Profile list. 0x15(Default). + 0x01:LPDDR3_1333_10_12_12, 0x02:LPDDR3_1600_12_15_15, 0x03:LPDDR3_1866_14_17_17, + 0x04:LPDDR4_1600_14_15_15, 0x05:LPDDR4_1866_20_17_17, 0x06:LPDDR4_2133_20_20_20, + 0x07:LPDDR4_2400_24_22_22, 0x08:LPDDR4_2666_24_24_24, 0x09:LPDDR4_3200_28_29_29, + 0x0A:DDR4_1600_10_10_10, 0x0B:DDR4_1600_11_11_11, 0x0C:DDR4_1600_12_12_12, 0x0D:DDR4_1866_12_12_12, + 0x0E:DDR4_1866_13_13_13, 0x0F:DDR4_1866_14_14_14, 0x10:DDR4_2133_14_14_14, 0x11:DDR4_2133_15_15_15, + 0x12:DDR4_2133_16_16_16, 0x13:DDR4_2400_15_15_15, 0x14:DDR4_2400_16_16_16, 0x15:DDR4_2400_17_17_17, + 0x16:DDR4_2400_18_18_18, 0x17:DDR4_2666_17_17_17, 0x18:DDR4_2666_18_18_18, 0x19:DDR4_2666_19_19_19, + 0x1A:DDR4_2666_20_20_20 **/ UINT8 Profile;
/** Offset 0x004F - MemoryDown Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L/4 only) ACRD, 0x3:1x32 LPDDR4 **/ UINT8 MemoryDown;
@@ -302,7 +298,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch0_DeviceWidth;
@@ -314,7 +310,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch0_DramDensity;
@@ -383,7 +379,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch1_DeviceWidth;
@@ -395,7 +391,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch1_DramDensity;
@@ -453,7 +449,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch2_DeviceWidth;
@@ -465,7 +461,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch2_DramDensity;
@@ -523,7 +519,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch3_DeviceWidth;
@@ -535,7 +531,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch3_DramDensity;
@@ -820,36 +816,26 @@ **/ UINT8 EnableS3Heci2;
-/** Offset 0x0152 +/** Offset 0x0152 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable, 2:Auto(Default). **/ - UINT8 ReservedFspmUpd[3]; + UINT8 PcieRootPortEn[6]; + +/** Offset 0x0158 - PCIE SLOT Power Enable Assert Time - PFET. + ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will + wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer + who designed the board PCIE slot Power automatically enabled, can pass value of + zero here. +**/ + UINT64 StartTimerTickerOfPfetAssert; + +/** Offset 0x0160 **/ + VOID* VariableNvsBufferPtr; + +/** Offset 0x0164 +**/ + UINT8 ReservedFspmUpd[4]; } FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0155 -**/ - UINT32 Signature; - -/** Offset 0x0159 -**/ - UINT8 ReservedFspmTestUpd[28]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0175 -**/ - UINT32 Signature; - -/** Offset 0x0179 -**/ - UINT8 ReservedFspmRestrictedUpd[124]; -} FSP_M_RESTRICTED_CONFIG;
/** Fsp M UPD Configuration **/ @@ -867,23 +853,16 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0155 +/** Offset 0x0168 **/ - FSP_M_TEST_CONFIG FspmTestConfig; + UINT8 UnusedUpdSpace1[150];
-/** Offset 0x0175 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01F5 -**/ - UINT8 UnusedUpdSpace1[14]; - -/** Offset 0x0203 +/** Offset 0x01FE **/ UINT16 UpdTerminator; } FSPM_UPD;
-#pragma pack(pop) +#pragma pack()
#endif + diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 081fb94..7f0bbe6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -35,7 +35,7 @@
#include <FspUpd.h>
-#pragma pack(push, 1) +#pragma pack(1)
/** Fsp S Configuration @@ -1522,161 +1522,122 @@ **/ UINT64 SgxEpoch1;
-/** Offset 0x0343 - Selective enable SGX - Selective enable SGX. 0xFFFF(Default). -**/ - UINT16 SelectiveEnableSgx; - -/** Offset 0x0345 - SGX debug mode - Select SGX mode. 0:Disable(default), 1:Enable - 0:Disable(default), 1:Enable -**/ - UINT8 SgxDebugMode; - -/** Offset 0x0346 - MicrocodePatchAddress +/** Offset 0x0343 - MicrocodePatchAddress MicrocodePatchAddress. 0x0(Default). **/ UINT64 MicrocodePatchAddress;
-/** Offset 0x034E - SGX Launch Control Policy Mode - Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default) - 0:Intel - Default, 1:Per-boot Select mode(default) -**/ - UINT8 LcpMode; - -/** Offset 0x034F - LE KeyHash0 - LE KeyHash0. 0x0(Default). -**/ - UINT64 SgxLeKeyHash0; - -/** Offset 0x0357 - LE KeyHash1 - LE KeyHash1. 0x0(Default). -**/ - UINT64 SgxLeKeyHash1; - -/** Offset 0x035F - LE KeyHash2 - LE KeyHash2. 0x0(Default). -**/ - UINT64 SgxLeKeyHash2; - -/** Offset 0x0367 - LE KeyHash3 - LE KeyHash3. 0x0(Default). -**/ - UINT64 SgxLeKeyHash3; - -/** Offset 0x036F - CNVi Mode +/** Offset 0x034B - CNVi Mode Selects CNVi Mode. 0:Disable, 1:Auto(Default). $EN_DIS **/ UINT8 CnviMode;
-/** Offset 0x0370 - BT Interface +/** Offset 0x034C - BT Interface CNVi BT interface. 0:UART, 1:USB(Default). $EN_DIS **/ UINT8 CnviBtInterface;
-/** Offset 0x0371 - Disable Sx Wake +/** Offset 0x034D - Disable Sx Wake Enables/Disables wake from Sx . 0:No(Default), 1:Yes. $EN_DIS **/ - UINT8 PowerRailMerge; + UINT8 DisableSxWake;
-/** Offset 0x0372 - ModifyCrfGpios +/** Offset 0x034E - ModifyCrfGpios Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration of GNSS and BtOnUart gpios will/will not be done based on this policy $EN_DIS **/ UINT8 ModifyCrfGpios;
-/** Offset 0x0373 - dGPU Hold Reset +/** Offset 0x034F - dGPU Hold Reset dGPU Hold Reset GPIO information from GPIO community, Pin and Active **/ UINT8 HgDgpuHoldRst[8];
-/** Offset 0x037B - dGPU Power Enable +/** Offset 0x0357 - dGPU Power Enable dGPU power enable GPIO information from GPIO community, Pin and Active **/ UINT8 HgDgpuPwrEnable[8];
-/** Offset 0x0383 - dGPU Delay after power enable +/** Offset 0x035F - dGPU Delay after power enable Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum , 300 : Default 0 : Minimum , 1000 : Maximum , 300 : Default **/ UINT16 HgDelayAfterPwrEn;
-/** Offset 0x0385 - dGPU Delay after hold reset +/** Offset 0x0361 - dGPU Delay after hold reset Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum , 100 : Default 0 : Minimum , 1000 : Maximum , 100 : Default **/ UINT16 HgDelayAfterHoldReset;
-/** Offset 0x0387 - HG Enable +/** Offset 0x0363 - HG Enable Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable 0x1:Enabled, 0x0:Disabled **/ UINT8 HgEnabled;
-/** Offset 0x0388 - PAVP ASMF +/** Offset 0x0364 - PAVP ASMF Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 PavpAsmf;
-/** Offset 0x0389 - CpuS3ResumeMtrrDataSize +/** Offset 0x0365 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data. **/ UINT16 CpuS3ResumeMtrrDataSize;
-/** Offset 0x038B - CpuS3ResumeMtrrData +/** Offset 0x0367 - CpuS3ResumeMtrrData Pointer CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData;
-/** Offset 0x038F - PAVP Auto TearDown Grace Period Enable +/** Offset 0x036B - PAVP Auto TearDown Grace Period Enable Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 AutoTearDownGracePeriod;
-/** Offset 0x0390 - SeC EndOfPost EnableDisable +/** Offset 0x036C - SeC EndOfPost EnableDisable Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 EndOfPostEnabled;
-/** Offset 0x0391 +/** Offset 0x036D - EnableDigitalThermalSensor EnableDisable + Enable/Disable EnableDigitalThermalSensor 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 EnableDigitalThermalSensor; + +/** Offset 0x036E - PNP Mode + Select PNP Mode. 0:Disable,1:Power,2:Performance,3:Power&Performance + 0:Disable,1:Power,2:Performance,3:Power&Performance(default) +**/ + UINT8 PnpSettings; + +/** Offset 0x036F - OsBoot EnableDisable + Select OsBoot. 1:EMMC boot, 0:HardDisk boot + 1:EMMC boot, 1:HardDisk boot +**/ + UINT8 OsBoot; + +/** Offset 0x0370 - AP threads Idle Manner + AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP + $EN_DIS +**/ + UINT8 ApIdleManner; + +/** Offset 0x0371 **/ UINT8 ReservedFspsUpd[3]; } FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0394 -**/ - UINT32 Signature; - -/** Offset 0x0398 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x03A4 -**/ - UINT32 Signature; - -/** Offset 0x03A8 -**/ - UINT8 ReservedFspsRestrictedUpd[2]; -} FSP_S_RESTRICTED_CONFIG;
/** Fsp S UPD Configuration **/ @@ -1690,19 +1651,16 @@ **/ FSP_S_CONFIG FspsConfig;
-/** Offset 0x0394 +/** Offset 0x0374 **/ - FSP_S_TEST_CONFIG FspsTestConfig; + UINT8 UnusedUpdSpace7[58];
-/** Offset 0x03A4 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x03AA +/** Offset 0x03AE **/ UINT16 UpdTerminator; } FSPS_UPD;
-#pragma pack(pop) +#pragma pack()
#endif +