Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/62566/comment/5fdfc3ea_3b531283
PS2, Line 164: MP_SERVICES_PPI
I have access to one ADL-N RVP board, that shows some sluggishness in depthcharge. I will pick this CL and try.
I have reconfirmed that the I'm seeing sluggishness with this CL cherry picked and followed by TPM I2C read operation failure (I don't know what is the relation between those two at this moment, but this is the observation), last that also I had seen the same failure and my board went down, hence reconfirmed again.
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