[coreboot-gerrit] Change in coreboot[master]: Enable long cr50 ready pulses for Tigerlake systems

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )

Change subject: Enable long cr50 ready pulses for Tigerlake systems
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Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43741/6/src/drivers/spi/tpm/tpm.c 
File src/drivers/spi/tpm/tpm.c:

https://review.coreboot.org/c/coreboot/+/43741/6/src/drivers/spi/tpm/tpm.c@6... 
PS6, Line 662: 		if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/43741/6/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43741/6/src/soc/intel/tigerlake/fsp... 
PS6, Line 210:         /* S0iX: Selectively enable individual sub-states.
code indent should use tabs where possible