[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Well, if each bit corresponds to one PCI function, then we might as well check the corresponding dev […]

Ok, looking back, TGL-U/Y seems to only has one CPU-side PCIe root port (00:06.00), so that would make sense to tie this to the device enabled state.