Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35880 )
Change subject: kbl boards / fsp2.0: remove redundant CdClock setting ......................................................................
kbl boards / fsp2.0: remove redundant CdClock setting
CdClock for KabyLake FSP2.0 already defaults to 3. Hence, don't set it again.
Change-Id: Ie3bd7f3dc4c795691a04d2eaba0e2458ee50aabb Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/asrock/h110m/ramstage.c M src/mainboard/intel/kblrvp/ramstage.c 2 files changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35880/1
diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index a247b72..93b926d 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -22,6 +22,4 @@ /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - params->CdClock = 3; } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index a19e96e..646a4ac 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -24,7 +24,6 @@ /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - params->CdClock = 3; }
static void ioexpander_init(void *unused)