[coreboot-gerrit] Change in coreboot[master]: soc/skylake: Enable DCI depending on devicetree configuration

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43846 )

Change subject: soc/skylake: Enable DCI depending on devicetree configuration
......................................................................

soc/skylake: Enable DCI depending on devicetree configuration

Currently DCI gets enabled by the option PchDciEn, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the DCI controller.

I checked all corresponding mainboards if the devicetree
configuration matches the PchDciEn setting.

Change-Id: Ic816655d87cee9e56520aa30fc3c837b561f24e5
Signed-off-by: Felix Singer 
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/romstage/romstage.c
2 files changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/43846/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 92cd1ba..06dc59d 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -194,9 +194,6 @@
    u32 TraceHubMemReg0Size;
    u32 TraceHubMemReg1Size;

-	/* DCI Enable/Disable */
-	u8 PchDciEn;
-
    /*
     * PCIe Root Port configuration:
     * each element of array corresponds to
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 99f444a..cb3f5b9 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -291,7 +291,8 @@
    m_t_cfg->DidInitStat = 0x01;

/* DCI and TraceHub configs */
-	m_t_cfg->PchDciEn = config->PchDciEn;
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
+	m_t_cfg->PchDciEn = dev ? dev->enabled : 0;
    m_cfg->EnableTraceHub = config->EnableTraceHub;
    m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
    m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;