Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48080 )
Change subject: mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG@12 PS4, Line 12: Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low
As per HW team recommendation, this PINs should drive low to get card detected on x1 DT slot
I think it would be good to add a comment to indicate that this is a RVP specific requirement so that it doesn't get copied over to other boards.
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 54: free running CLK
RP8 has CLK6 as source and CLK7 as req. […]
I still don't understand this. Why not set PcieClkSrcUsage[5]="7" so that CLK SRC 6 is configured for RP8?