Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63569 )
Change subject: soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOW/HIGH_LOCK macro ......................................................................
soc/intel/common/gpio: Add PAD_CFG_GPI_SCI_LOW/HIGH_LOCK macro
Add PAD_CFG_GPI_SCI_LOW_LOCK and PAD_CFG_GPI_SCI_HIGH_LOCK macro to support mainboard to lock NC and GPI_SCI pins as applicable.
BUG=b:216583542 TEST=build passed
Signed-off-by: Eric Lai eric_lai@quanta.corp-partner.google.com Change-Id: I5060777cc09af6cb3144ad799154e77167521de3 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63569/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 32a7d6b..efa960c 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -452,9 +452,15 @@ #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
+#define PAD_CFG_GPI_SCI_LOW_LOCK(pad, pull, trig, lock_action) \ + PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, INVERT, lock_action) + #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
+#define PAD_CFG_GPI_SCI_HIGH_LOCK(pad, pull, trig, lock_action) \ + PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, NONE, lock_action) + #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ _PAD_CFG_STRUCT_3(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \