Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42440/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42440/3//COMMIT_MSG@9 PS3, Line 9: Add PchPmPwrCycDur to chip options to control the UPD : FSPS PchPmPwrCycDur from devicetree. The UPD determines the : minimum time a platform will stay in reset during host partition : reset with power cycle or global reset. Please re-flow for 75 characters per line.
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... PS3, Line 319: * 4 = 4sec (default) SI unit is *s*.
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch... PS3, Line 321: uint8_t PchPmPwrCycDur; `src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h` says that 0 is the default.
``` /** Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; ```
Also, all non-negative integers could be used?