[coreboot-gerrit] [L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4

[Riku Viitanen (Code Review)]

Attention is currently required from: Angel Pons.

Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email )

Change subject: mb/asrock: Add Z77 Extreme4
......................................................................

Patch Set 4:

(5 comments)

File src/mainboard/asrock/z77_extreme4/cmos.layout:

https://review.coreboot.org/c/coreboot/+/85772/comment/0360f251_ea4c6067?usp... :
PS3, Line 27:  Sandy Bridge MRC Scrambler Seed values
            : 896	32	r	0	mrc_scrambler_seed
            : 928	32	r	0	mrc_scrambler_seed_s3
            : 960	16	r	0	mrc_scrambler_seed_chk
> Only used with MRC.bin and this board is native-only. Please remove.

Done

File src/mainboard/asrock/z77_extreme4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/85772/comment/2020bd96_aa6ba64f?usp... :
PS3, Line 16: # bifurcated from peg10
> It is, by design. The PCIe lanes can't come from any other place.

Done

File src/mainboard/asrock/z77_extreme4/dsdt.asl:

https://review.coreboot.org/c/coreboot/+/85772/comment/7c8429f0_14fcc52a?usp... :
PS3, Line 10: // OEM revision
> Looks like autoport copypasta, please remove if so

Done

https://review.coreboot.org/c/coreboot/+/85772/comment/230d6858_eda2f287?usp... :
PS3, Line 21: Scope (_SB) {
            : 		Device (PCI0)
            : 		{
            : 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
            : 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
            : 		}
            : 	}
> nit: Old autoport versions used to emit this incoherent use of tabs and brace location. […]

Done

File src/mainboard/asrock/z77_extreme4/mainboard.c:

PS3:
> Was VBIOS tested?

no