Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33768
Change subject: soc/amd/picasso: Reduce 48M out configuration ......................................................................
soc/amd/picasso: Reduce 48M out configuration
Picasso has only a single 48M output. Simplify the setup function.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 --- M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 2 files changed, 4 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/33768/1
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 04e9a25..4a7f730 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -175,8 +175,7 @@ #define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) -#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ -#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ +#define BP_X48M0_OUTPUT_EN BIT(2) /* 0 = Enabled, 1 = Disabled */
/* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 @@ -313,7 +312,7 @@ };
void enable_aoac_devices(void); -void sb_clk_output_48Mhz(u32 osc); +void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index f487d08..f1616ab 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -189,26 +189,12 @@ pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); }
-void sb_clk_output_48Mhz(u32 osc) +void sb_clk_output_48Mhz(void) { u32 ctrl;
- /* - * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) - * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. - */ ctrl = misc_read32(MISC_CLK_CNTL1); - - switch (osc) { - case 1: - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; - break; - case 2: - ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; - break; - default: - return; /* do nothing if invalid */ - } + ctrl |= BP_X48M0_OUTPUT_EN; misc_write32(MISC_CLK_CNTL1, ctrl); }