[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )

Change subject: arch/x86: Cache the TSEG region at the top of ram
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Patch Set 4:
> Patch Set 4:
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> I don't think we should do this unconditionally. I think it's going to depend on CAR implementation and uarch -- it's platform dependent, and we know that the current code doesn't explicitly flush all DRAM it's touching during loading.

Do you want it conditionally enabled even within the platform, intel/cannonlake here?