Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Jonathan Zhang, John Zhao, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44998
to review the following change.
Change subject: Revert "soc/intel/xeon_sp: Improve performance efficiencies" ......................................................................
Revert "soc/intel/xeon_sp: Improve performance efficiencies"
This reverts commit d51449d017410fedb55e93f71fb322749ba888b5.
Reason for revert: https://qa.coreboot.org/job/coreboot/16544/
Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44998/1
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1b6f1a3..cd497c5 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -605,16 +605,16 @@ * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, + int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) {
if (get_stack_for_port(port) != stack) return 0;
- const uint32_t bus = iio_resource->StackRes[stack].BusBase; - const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource.StackRes[stack].BusBase; + const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function;
const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -703,8 +703,8 @@
// Add PCIe Ports if (socket != 0 || stack != CSTACK) { - const IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, iio_resource, pcie_seg, false, NULL); @@ -748,12 +748,12 @@ uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; unsigned long tmp = current; bool first = true; - const IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket];
for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = iio_resource->StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); @@ -821,10 +821,10 @@ assert(hob != NULL && hob_size != 0);
for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue;