[coreboot-gerrit] [S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support

[Jayvik Desai (Code Review)]

Jayvik Desai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email )

Change subject: ec/google/chromeec: Add indexed IO support
......................................................................

ec/google/chromeec: Add indexed IO support

Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.

BUG=b:379224648
TEST= able to build nissa/yaviks

Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai 
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/ec_lpc.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85449/1

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index f0418ff..e7e56fa 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -60,6 +60,18 @@
      this option simply enables the LPC EC code.  The eSPI device
      still needs to correctly configure the bus transactions.

+config EC_GOOGLE_CHROMEEC_INDEXED_IO
+	depends on EC_GOOGLE_CHROMEEC && ARCH_X86
+	def_bool n
+	help
+	  Google Chrome EC enable support for indexed I/O access.
+
+	  Indexed I/O allows devices with multiple memory locations to be
+	  accessed using a single I/O port base address and an index register.
+	  A separate data register, typically located at the address
+	  immediately following the index register, is used for sending and
+	  receiving data to the device.
+
 config EC_GOOGLE_CHROMEEC_LPC
    depends on ARCH_X86  # Needs Plug-and-play.
    def_bool n
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 2a9eabb..1732abf 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -52,6 +52,18 @@
    return byte;
 }

+#if CONFIG(EC_GOOGLE_CHROMEEC_INDEXED_IO)
+/* Read singe byte and return byte read using indexed IO*/
+static inline u8 read_byte_indexed_io(u16 port, u8 offset)
+{
+	u8 byte;
+	outb(offset, port);
+	port = port + 1;
+	byte = inb(port);
+	return byte;
+}
+#endif
+
 /*
  * Write bytes to a given LPC-mapped address.
  *
@@ -156,6 +168,10 @@
    	printk(BIOS_ERR, "Error reading memmap data.\n");
    	return -1;
    }
+#elif CONFIG(EC_GOOGLE_CHROMEEC_INDEXED_IO)
+	id1 = read_byte_indexed_io(EC_LPC_ADDR_MEMMAP, EC_MEMMAP_ID);
+	id2 = read_byte_indexed_io(EC_LPC_ADDR_MEMMAP, EC_MEMMAP_ID + 1);
+	flags = read_byte_indexed_io(EC_LPC_ADDR_MEMMAP, EC_MEMMAP_HOST_CMD_FLAGS);
 #else
    id1 = read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID);
    id2 = read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1);