[coreboot-gerrit] Change in coreboot[master]: mb/google/jecht: Use Haswell CPU code

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46946 )

Change subject: mb/google/jecht: Use Haswell CPU code
......................................................................

mb/google/jecht: Use Haswell CPU code

Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475
Signed-off-by: Angel Pons 
---
M src/mainboard/google/jecht/Kconfig
M src/mainboard/google/jecht/devicetree.cb
2 files changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46946/1

diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index 4851bd7..7d6ff8d 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -1,5 +1,6 @@
 config BOARD_GOOGLE_BASEBOARD_JECHT
    def_bool n
+	select CPU_INTEL_HASWELL
    select SOC_INTEL_BROADWELL
    select BOARD_ROMSIZE_KB_8192
    select SUPERIO_ITE_IT8772F
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 94fd804..08b2c95 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -10,7 +10,10 @@
    register "gpu_dp_b_hotplug" = "0x06"

device cpu_cluster 0 on
-		device lapic 0 on end
+		chip cpu/intel/haswell
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
    end

device domain 0 on