Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30783
Change subject: amdfam10 boards: Simplify early resourcemap ......................................................................
amdfam10 boards: Simplify early resourcemap
Purpose of the table is to load initial address maps on PCI function 0:18.1. Provide a macro of its own so it is clear no other PCI devfn is accessed here.
Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/advansus/a785e-i/resourcemap.c M src/mainboard/amd/bimini_fam10/resourcemap.c M src/mainboard/amd/mahogany_fam10/resourcemap.c M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c M src/mainboard/amd/tilapia_fam10/resourcemap.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/m4a78-em/resourcemap.c M src/mainboard/asus/m4a785-m/resourcemap.c M src/mainboard/asus/m5a88-v/resourcemap.c M src/mainboard/avalue/eax-785e/resourcemap.c M src/mainboard/gigabyte/ma785gm/resourcemap.c M src/mainboard/gigabyte/ma785gmt/resourcemap.c M src/mainboard/gigabyte/ma78gm/resourcemap.c M src/mainboard/iei/kino-780am2-fam10/resourcemap.c M src/mainboard/jetway/pa78vm5/resourcemap.c M src/mainboard/msi/ms9652_fam10/resourcemap.c M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c M src/mainboard/supermicro/h8qme_fam10/resourcemap.c M src/mainboard/supermicro/h8scm_fam10/resourcemap.c M src/mainboard/tyan/s2912_fam10/resourcemap.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/resourcemap.c 24 files changed, 1,072 insertions(+), 1,067 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30783/1
diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c index 8390f49..ba264f3 100644 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ b/src/mainboard/advansus/a785e-i/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index ce4351f..84897db 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,13 +87,13 @@ */
/* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -127,13 +127,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,13 +161,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -194,9 +194,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -223,9 +223,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -264,9 +264,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 2a2380a..2c5c907 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CAR with FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CAR with FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 37b6d20..d51e128 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 0edc3d1..0dd0a9f 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
@@ -306,14 +306,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -345,14 +345,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -386,14 +386,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -421,14 +421,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -455,10 +455,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -485,10 +485,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -526,10 +526,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index 3591488..9efc60c 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c index b3c4465..cc3a23a 100644 --- a/src/mainboard/asus/kgpe-d16/resourcemap.c +++ b/src/mainboard/asus/kgpe-d16/resourcemap.c @@ -51,14 +51,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -90,14 +90,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -131,14 +131,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,14 +166,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -200,10 +200,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -271,10 +271,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
@@ -306,14 +306,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -345,14 +345,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -386,14 +386,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -421,14 +421,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -455,10 +455,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -485,10 +485,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -526,10 +526,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/asus/m4a78-em/resourcemap.c +++ b/src/mainboard/asus/m4a78-em/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/asus/m4a785-m/resourcemap.c +++ b/src/mainboard/asus/m4a785-m/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c index 94ada1e..85ba50b 100644 --- a/src/mainboard/asus/m5a88-v/resourcemap.c +++ b/src/mainboard/asus/m5a88-v/resourcemap.c @@ -47,14 +47,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -85,14 +85,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,14 +126,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,14 +161,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -195,10 +195,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -225,10 +225,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -266,10 +266,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c index 8390f49..ba264f3 100644 --- a/src/mainboard/avalue/eax-785e/resourcemap.c +++ b/src/mainboard/avalue/eax-785e/resourcemap.c @@ -48,13 +48,13 @@ * that define the end of the DRAM region. */ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -86,13 +86,13 @@ * that define the start of the DRAM region. */ /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -126,13 +126,13 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -160,13 +160,13 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,9 +193,9 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -222,9 +222,9 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -263,9 +263,9 @@ * This field defines the highest bus number in configuration regin i */ /* AMD 8111 on link0 of CPU 0 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c +++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c index da7fc1b..1162d54 100644 --- a/src/mainboard/jetway/pa78vm5/resourcemap.c +++ b/src/mainboard/jetway/pa78vm5/resourcemap.c @@ -50,14 +50,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c index 59155c6..7f8daac 100644 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,11 +198,11 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00004000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00004000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,11 +230,11 @@ * [31:25] Reserved */ /* Verified against board configuration registers after normal proprietary BIOS boot */ - //PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + //ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001033, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -273,10 +273,10 @@ * This field defines the highest bus number in configuration region i */ /* Verified against board configuration registers after normal proprietary BIOS boot */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 7dc4df1..55126d9 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -272,10 +272,10 @@ * This field defines the highest bus number in configuration region i */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 7dc4df1..55126d9 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -230,10 +230,10 @@ * [31:25] Reserved */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -272,10 +272,10 @@ * This field defines the highest bus number in configuration region i */ // WARD CHANGED - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c index a4a1d92..e7a8cbf 100644 --- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index f02d6a7..51e257d 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -49,14 +49,14 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ * This field defines the upp address bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, +// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, +// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00007000, +// ADDRMAP_REG(0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, +// ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00008033, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ +// ADDRMAP_REG(0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 163d9df..e1c88c9 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -26,6 +26,11 @@ struct DCTStatStruc; struct MCTStatStruc;
+ +/* Definitions for setup_resourcemap() variants. */ + +#define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) + #define RES_PCI_IO 0x10 #define RES_PORT_IO_8 0x22 #define RES_PORT_IO_32 0x20 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 362872b..fa4ab3c 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -45,14 +45,14 @@ * This field defines the upper address bits of a 40 bit * address that define the end of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -83,14 +83,14 @@ * This field defines the upper address bits of a 40-bit * address that define the start of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -125,14 +125,14 @@ * address that defines the end of a memory-mapped * I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,14 +161,14 @@ * address that defines the start of memory-mapped * I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -195,10 +195,10 @@ * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -270,10 +270,10 @@ * This field defines the highest bus number in * configuration regin i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, };
u32 max;