[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46787 )

Change subject: nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN
......................................................................

nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN

There's no need to perform manual shifting and masking when ACPI allows
one to painlessly describe bitfields of a register. The now-unused DVEN
definition will be dropped in a follow-up, alongside other definitions.

Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/haswell/acpi/peg.asl
1 file changed, 12 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl
index 8dac128..c63f3f9 100644
--- a/src/northbridge/intel/haswell/acpi/peg.asl
+++ b/src/northbridge/intel/haswell/acpi/peg.asl
@@ -1,12 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+Field (_SB.PCI0.MCHC.MCHP, DWordAcc, NoLock, Preserve)
+{
+	Offset (0x54),
+	,	1,
+	P2EN,	1,
+	P1EN,	1,
+	P0EN,	1,
+}
+
 Device (PEGP)
 {
    Name (_ADR, 0x00010000)

Method (_STA)
    {
-		Return (((_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf)
+		Return (P0EN * 0xf)
    }

Device (DEV0)
@@ -21,7 +30,7 @@

Method (_STA)
    {
-		Return (((_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf)
+		Return (P1EN * 0xf)
    }

Device (DEV0)
@@ -36,7 +45,7 @@

Method (_STA)
    {
-		Return (((_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf)
+		Return (P2EN * 0xf)
    }

Device (DEV0)