Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42661 )
Change subject: sb/intel/bd82x6x: Use common early SPI code ......................................................................
sb/intel/bd82x6x: Use common early SPI code
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/bd82x6x/bootblock.c 1 file changed, 2 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 3a99f51..a3228e7 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -2,16 +2,9 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "pch.h"
-/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCH_LPC_DEV, BIOS_CNTL, ~(3 << 2), 2 << 2); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -40,7 +33,7 @@
void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching();
early_pch_init();