[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Enable debug driver for Alder Lake platform

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62652 )

Change subject: soc/intel/alderlake: Enable debug driver for Alder Lake platform
......................................................................

soc/intel/alderlake: Enable debug driver for Alder Lake platform

The patch enables dynamic debug capability driver for Alder Lake
platform.

TEST= Build code for Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62652/1

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ae83d49..4fccc35 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -9,6 +9,7 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <intelblocks/thermal.h>
+#include <intelblocks/debug_feature.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -134,6 +135,9 @@
    /* Initialize HECI interface */
    heci_init(HECI1_BASE_ADDRESS);

+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE))
+		pre_mem_debug_init();
+
    s3wake = pmc_fill_power_state(ps) == ACPI_S3;

if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {