[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add config for Enbaling PCIe AER

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21401

Change subject: soc/intel/skylake: Add config for Enbaling PCIe AER
......................................................................

soc/intel/skylake: Add config for Enbaling PCIe AER

Add a config for enabling/disabling Advanced Error Reporting feature
for PCIe root ports.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21401/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index beb5a7a..45f3f99 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -173,6 +173,7 @@
    u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
    u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
    u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+	u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];

/* USB related */
    struct usb2_port_config usb2_ports[16];
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index aa612ed..adf8772 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -166,6 +166,9 @@
           sizeof(params->PcieRpClkReqSupport));
    memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
           sizeof(params->PcieRpClkReqNumber));
+	memcpy(params->PcieRpAdvancedErrorReporting,
+		config->PcieRpAdvancedErrorReporting,
+			sizeof(params->PcieRpAdvancedErrorReporting));

/* disable Legacy PME */
    memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));