[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Fix bootblock size with CBnT

[Arthur Heymans (Code Review)]

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Angel Pons.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50082 )

Change subject: soc/intel/xeon_sp/cpx: Fix bootblock size with CBnT
......................................................................

Patch Set 1:

(2 comments)

File src/soc/intel/xeon_sp/cpx/Kconfig:

https://review.coreboot.org/c/coreboot/+/50082/comment/e0d24284_3bd99ae3 
PS1, Line 9: 	select FIXED_BOOTBLOCK_SIZE if INTEL_CBNT_SUPPORT
> Shouldn't this be selected the other way around? Make INTEL_CBNT_SUPPORT select FIXED_BOOTBLOCK_SIZE

That makes more sense indeed.

https://review.coreboot.org/c/coreboot/+/50082/comment/04712717_32622ef9 
PS1, Line 69: IBB
> The IBB consist of more than just the bootblock.

It's whatever is set up in the BPM. Currently we use the top 0xc000 as IBB on the ocp/deltalake.