Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5947
-gerrit
commit e84d28b46c7dcce0f7a5e4fc93906eb850c59873 Author: Dave Frodin dave.frodin@se-eng.com Date: Thu Jun 5 14:30:22 2014 -0600
amd/southbridge/lpc: Fix how the SPI BAR is configured
The code was treating the LPC SPI BAR as a normal PCI BAR. This will set the resources for a fixed size at a fixed address.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/southbridge/amd/agesa/hudson/hudson.h | 5 +++++ src/southbridge/amd/agesa/hudson/lpc.c | 15 +++++++++------ src/southbridge/amd/cimx/sb800/lpc.c | 14 ++++++++++---- src/southbridge/amd/cimx/sb800/lpc.h | 5 +++++ 4 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 6f757eb..555b81b 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,6 +52,10 @@ #define REV_HUDSON_A12 0x12
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPI_ROM_ENABLE 0x02 +#ifndef SPI_BASE_ADDRESS + #define SPI_BASE_ADDRESS 0xFEC10000 +#endif
#ifndef __SMM__
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 71aaf6f..b22a4d2 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -87,8 +87,6 @@ static void hudson_lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; @@ -102,6 +100,13 @@ static void hudson_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add an memory resource for the SPI BAR. */ + res = new_resource(dev, 2); + res->base = SPI_BASE_ADDRESS; + res->size = 0x20; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -115,12 +120,10 @@ static void hudson_lpc_set_resources(struct device *dev) struct resource *res;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); - res->base |= PCI_COMMAND_MEMORY; + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev); - - }
/** diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a1e0dc9..03f000a 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,8 +34,6 @@ void lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; @@ -48,6 +47,13 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add an memory resource for the SPI BAR. */ + res = new_resource(dev, 2); + res->base = SPI_BASE_ADDRESS; + res->size = 0x20; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -64,8 +70,8 @@ void lpc_set_resources(struct device *dev) printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); - res->base |= PCI_COMMAND_MEMORY; + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev);
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 575b9f7..f8466b0 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,10 @@ #define _SB800_LPC_H_
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */ +#define SPI_ROM_ENABLE 0x02 +#ifndef SPI_BASE_ADDRESS + #define SPI_BASE_ADDRESS 0xFEC10000 +#endif
void lpc_read_resources(device_t dev); void lpc_set_resources(device_t dev);