[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email )

Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................

soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting

According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.

But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A),
hence, provide a config for projects modification.

BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
     to observe whether the value is changing as expected.

Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Derek Huang 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 15 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Derek Huang: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index b58b244..ec6c0f5 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -777,6 +777,16 @@
     * Set this to 0 in order to disable hwp scalability tracking.
     */
    bool enable_hwp_scalability_tracking;
+
+	/*
+	 * (ADL-N/TWL only) Vccin Aux Imon Iccmax
+	 * Defaults to 27000 (27A), the value has to align with HW design.
+	 * Recommended value: 25000 (PD_TIER_PREMIUM) or 27000 (PD_TIER_VOLUME)
+	 */
+	enum {
+		PD_TIER_PREMIUM = 25000,
+		PD_TIER_VOLUME  = 27000
+	} vccin_aux_imon_iccmax;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index dd66f8f..8dca5b0 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -560,7 +560,7 @@

/* This function returns the VccIn Aux Imon IccMax values for ADL and RPL
    SKU's */
-static uint16_t get_vccin_aux_imon_iccmax(void)
+static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_config *config)
 {
    struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
    uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
@@ -596,7 +596,8 @@
    case PCI_DID_INTEL_ADL_N_ID_3:
    case PCI_DID_INTEL_ADL_N_ID_4:
    case PCI_DID_INTEL_ADL_N_ID_5:
-		return ICC_MAX_ID_ADL_N_MA;
+		return config->vccin_aux_imon_iccmax
+			? config->vccin_aux_imon_iccmax : ICC_MAX_ID_ADL_N_MA;
    case PCI_DID_INTEL_ADL_S_ID_1:
    case PCI_DID_INTEL_ADL_S_ID_3:
    case PCI_DID_INTEL_ADL_S_ID_8:
@@ -1063,7 +1064,8 @@
    s_cfg->EnergyEfficientTurbo = 0;

/* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */
-	s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS;
+	s_cfg->VccInAuxImonIccImax =
+		get_vccin_aux_imon_iccmax(config) * 4 / MILLIAMPS_TO_AMPS;

/* VrConfig Settings for IA and GT domains */
    for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)