[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-T in long mode

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81281?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
......................................................................

drivers/intel/fsp2_0: Support FSP-T in long mode

Call into FSP-T using the protected mode wrapper
and enter long mode in FSP-T support assembly code.

TEST: Booted on ibm/sbp1 in long mode.

Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/drivers/intel/fsp2_0/temp_ram_exit.c
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
2 files changed, 20 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c
index 87b77bc..86cc216 100644
--- a/src/drivers/intel/fsp2_0/temp_ram_exit.c
+++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c
@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <arch/romstage.h>
+#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
-#include <cbfs.h>
+#include <mode_switch.h>
 #include <types.h>

static void fsp_temp_ram_exit(void)
@@ -25,9 +26,12 @@
    if (fsp_validate_component(&hdr, mapping, size) != CB_SUCCESS)
    	die("Invalid FSPM header!\n");

-	temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry_offset);
+	temp_ram_exit = (void *)(uintptr_t)(hdr.image_base + hdr.temp_ram_exit_entry_offset);
    printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit);
-	status = temp_ram_exit(NULL);
+	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
+		status = protected_mode_call_1arg(temp_ram_exit, (uintptr_t)NULL);
+	else
+		status = temp_ram_exit(NULL);

if (status != FSP_SUCCESS)
    	die("TempRamExit returned with error 0x%08x!\n", status);
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 238a57e..c6d2a9c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

-#include <device/pci_def.h>
+#include <cpu/x86/64bit/entry64.inc>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/post_code.h>
+#include <device/pci_def.h>
 #include <intelblocks/post_codes.h>

#define CBFS_FILE_MAGIC 0
@@ -15,6 +16,8 @@

.extern	temp_ram_init_params

+.code32
+
 .global	bootblock_pre_c_entry
 bootblock_pre_c_entry:

@@ -88,10 +91,19 @@
    pop	%ecx
    movl	%ecx, temp_memory_start

+#if ENV_X86_64
+	setup_longmode $PM4LE
+	movl	%ebp, %edi
+	shlq	$32, %rdi
+	movd	%mm1, %rsi
+	or	%rsi, %rdi
+	andl	$0xfffffff0, %esp
+#else
    /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
    push	%ebp
    movd	%mm1, %eax
    push	%eax
+#endif

/* Copy .data section content to Cache-As-Ram */
 #include <cpu/x86/copy_data_section.inc>