Attention is currently required from: Felix Held, Jérémy Compostella, Shuo Liu.
yuchi.chen@intel.com has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email )
Change subject: include/device/pci_def.h: Add PCIe SRIOV definitions
......................................................................
Patch Set 16:
(1 comment)
File src/include/device/pci_def.h:
https://review.coreboot.org/c/coreboot/+/83319/comment/d74df1e2_48d7a47a?usp... :
PS15, Line 587: #define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e
in the other definitions in this file, the value is tab-aligned; would be good to do that here too
Done
--
To view, visit
https://review.coreboot.org/c/coreboot/+/83319?usp=email
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013
Gerrit-Change-Number: 83319
Gerrit-PatchSet: 16
Gerrit-Owner: yuchi.chen@intel.com
Gerrit-Reviewer: Jérémy Compostella
jeremy.compostella@intel.com
Gerrit-Reviewer: Shuo Liu
shuo.liu@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Felix Held
felix-coreboot@felixheld.de
Gerrit-CC: Vasiliy Khoruzhick
vasilykh@arista.com
Gerrit-Attention: Jérémy Compostella
jeremy.compostella@intel.com
Gerrit-Attention: Shuo Liu
shuo.liu@intel.com
Gerrit-Attention: Felix Held
felix-coreboot@felixheld.de
Gerrit-Comment-Date: Wed, 04 Sep 2024 00:36:54 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Felix Held
felix-coreboot@felixheld.de