Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42934 )
Change subject: mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path ......................................................................
mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path
This change configures PCIE_RST1_L as GPO driven low on the sleep path. This is required to keep PERST# asserted to devices until coreboot deasserts it on S3 resume path. Without this change, on S3 resume, PCIE_RST1_L gets deasserted sooner than required resulting in violation of PCIe reset timings.
With this change, the behavior of PCIE_RST1_L is as follows: 1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot bootblock/romstage and driven high. 2. On S3 entry, GPIO27 is configured as GPO driven low.
* Boot out of G3: Timing should be met since GPIO_27 is pulled down by default until coreboot configures it. * S3 resume: Timing should be met since GPIO_27 is configured as GPO low and it retains state across S3 entry/exit. So, should be low until coreboot configures it. * Warm reset: Timing should be met since it is configured as NF. So, hardware guarantees the reset timing as seen in "warm reset.jpg" in #46.
BUG=b:152582706
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Aaron Durbin adurbin@google.com Commit-Queue: Furquan Shaikh furquan@chromium.org Tested-by: Furquan Shaikh furquan@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/42934 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index e43b0b4c..1dd2dd5 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -34,6 +34,8 @@ static const struct soc_amd_gpio gpio_sleep_table[] = { /* PEN_POWER_EN */ PAD_GPO(GPIO_5, LOW), + /* PCIE_RST1_L */ + PAD_GPO(GPIO_27, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), };