[coreboot-gerrit] [S] Change in coreboot[master]: mb/amd/mayan: Enable MXM PCIe slot

[Anand Vaikar (Code Review)]

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74308 )

Change subject: mb/amd/mayan: Enable MXM PCIe slot
......................................................................

mb/amd/mayan: Enable MXM PCIe slot

Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b
Signed-off-by: Anand Vaikar 
---
M src/mainboard/amd/mayan/devicetree_phoenix.cb
M src/mainboard/amd/mayan/ec.c
M src/mainboard/amd/mayan/port_descriptors.c
3 files changed, 40 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74308/1

diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb
index 9d1a4b3..1595987 100644
--- a/src/mainboard/amd/mayan/devicetree_phoenix.cb
+++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb
@@ -158,6 +158,7 @@

device domain 0 on
    	device ref iommu on end
+		device ref gpp_bridge_1_1 on end # MXM
    	device ref gpp_bridge_2_1 on end # GBE
    	device ref gpp_bridge_2_2 on end # WIFI
    	device ref gpp_bridge_2_3 on end # NVMe SSD
diff --git a/src/mainboard/amd/mayan/ec.c b/src/mainboard/amd/mayan/ec.c
index 1b1d09b..e84cb8f 100644
--- a/src/mainboard/amd/mayan/ec.c
+++ b/src/mainboard/amd/mayan/ec.c
@@ -8,6 +8,12 @@
 #define MAYAN_EC_CMD		0x666
 #define MAYAN_EC_DATA		0x662

+#define EC_GPIO_1_ADDR		0xA1
+#define EC_GPIO_EVAL_PWREN	BIT(1)
+
+#define EC_GPIO_2_ADDR		0xA2
+#define EC_GPIO_EVAL_SLOT_PWR	BIT(5)
+
 #define EC_GPIO_3_ADDR		0xA3
 #define EC_GPIO_LOM_RESET_AUX	BIT(1)

@@ -35,8 +41,18 @@
 {
    uint8_t tmp;

+	/*Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR
+	and EC_GPIO_EVAL_RST_AUX */
+	tmp = ec_read(EC_GPIO_1_ADDR);
+	tmp |= EC_GPIO_EVAL_PWREN;
+	ec_write(EC_GPIO_1_ADDR, tmp);
+
+	tmp = ec_read(EC_GPIO_2_ADDR);
+	tmp |= EC_GPIO_EVAL_SLOT_PWR;
+	ec_write(EC_GPIO_2_ADDR, tmp);
+
    tmp = ec_read(EC_GPIO_3_ADDR);
-	tmp |= EC_GPIO_LOM_RESET_AUX;
+	tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX;
    ec_write(EC_GPIO_3_ADDR, tmp);

tmp = ec_read(EC_GPIO_7_ADDR);
diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c
index f52abcd..67cc538 100644
--- a/src/mainboard/amd/mayan/port_descriptors.c
+++ b/src/mainboard/amd/mayan/port_descriptors.c
@@ -10,17 +10,24 @@

static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
    {
+		// MXM
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
    	.start_logical_lane = 0,
-		.end_logical_lane = 0,
-		.device_number = 2,
+		.end_logical_lane = 3,
+		.device_number = 1,
    	.function_number = 1,
-		.link_speed_capability = GEN3,
+		.link_speed_capability = GEN_MAX,
    	.turn_off_unused_lanes = true,
    	.link_aspm = 2,
-		.link_hotplug = 3,
-		.clk_req = CLK_REQ3,
+		.link_aspm_L1_1 = 1,
+		.link_aspm_L1_2 = 1,
+		.link_hotplug = 0,
+		.gpio_group_id = 4,
+		.clk_pm_support = 1,
+		.clk_req = CLK_REQ0,
+		.eq_preset = 3,
+		.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}
    },
    {
    	.engine_type = PCIE_ENGINE,