Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG@9 PS6, Line 9: Ignore integrated GBE controller LTR setting to make it wake up from : s0ix with 10/100M cable attached.
Is that documented or is it a workaround? Why does Latency Tolerance Reporting cause problems?
Yes it is a workaround. https://elixir.bootlin.com/linux/latest/source/drivers/net/ethernet/intel/e1... in GBE is not actually a real LTR for PCIE. Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop latencies in the LTR Extended Capability Structure in the PCIe Extended Capability register set, on this device LTR is set by writing the equivalent snoop/no-snoop latencies in the LTRV register in the MAC and set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) message to the PMC.