[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63625 )

Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/63625/comment/aa0bc3d7_38e06690 
PS6, Line 437: SPIBAR_HSFSTS_W1C_BITS
> If I see it right here on EHL bit 15 is the flash lock config bit. Setting it here is not something you want, right? And there are other settings in the lower bits of MSB that are R/W which you will set with 0xffff as well.

Valid point, but looks like flashrom is doing the same
https://github.com/flashrom/flashrom/blob/master/ichspi.c#L1402

And I also think the risk is none with 0xFFFF as `fast_spi_lock_bar` function getting called right after `fast_spi_clear_outstanding_status()` is setting the BIT15 FLOCKDN.

CB:63777 to fix this issue, can you please check?