[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Sowmya Aralguppe, Wonkyu Kim.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )

Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
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Patch Set 13:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83946/comment/f332cec7_73e79609?usp... :
PS13, Line 28: 3
if one way size if 1.5MB (0x180000) then technically 3 way is enough to cover the mapping for 4.5MB (more than 4MB of CONFIG_DCACHE_RAM_SIZE)

I believe this effective way size calculation should be dependent of knowing if we are using LLC or MLC ? and if MLC then we need to use some other logic (may be what you have suggested) because MLC way size is always lesser than the LLC way size.