[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Paul Menzel (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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Patch Set 5:

(1 comment)

Patchset:

PS5:
> Also, why does the AGESA/FSP binary blob do the eDP tuning? Why can’t it be done properly in coreboo […]

Sorry, eDP is part of graphics initialization, which is currently not FLOSS on AMD hardware. Please document it better in the commit message, what part of FSP/AGESA does the eDP tuning. (GOP?)