Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.
Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80413?usp=email )
Change subject: soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config ......................................................................
soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled. Also this brings picasso inline with cezanne, mendocino and phoenix. This also prepares picasso to use the common function gpp_clk_setup_coomon.
Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396 Signed-off-by: Varshit Pandya pandyavarshit@gmail.com --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fch.c 3 files changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/80413/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3768cfb..5266e8a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -66,6 +66,7 @@ select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_SUPPORTS_WARM_RESET select SSE2 select UDK_2017_BINDING diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 0b65960..d0974a5 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -4,6 +4,7 @@ #define __PICASSO_CHIP_H__
#include <amdblocks/chip.h> +#include <amdblocks/pci_clk_req.h> #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> @@ -258,11 +259,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index bfe65a2..efa008d 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> @@ -174,7 +175,7 @@ /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_picasso_config *cfg = config_of_soc(); + struct soc_amd_picasso_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -189,6 +190,8 @@
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /*