Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra.
Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ......................................................................
Patch Set 50:
(10 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/70e33435_fa397870?usp... : PS38, Line 2:
Added all mentioned, except "SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID" Moved this config to ACPI CL.
SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID should be selected as part of this CL.
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/bd5dbd70_d5b9312d?usp... : PS50, Line 21: FSP_UGOP_EARLY_SIGN_OF_LIFE do you wish to select this now better add it when you have capable FSP to support uGOP?
https://review.coreboot.org/c/coreboot/+/83798/comment/93ca0af6_b0572eb8?usp... : PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 I don't believe the ME spec is 18 for PTL. Please submit the common code changes for cse_spec.c at first place to reflect the correct ME version for PTL.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83798/comment/f0620a62_4d719059?usp... : PS50, Line 43: PTL_U_404_15W_CORE, : PTL_H_484_25W_CORE, : PTL_H_484_45W_CORE, Why are you changing this macro? Without an explicit comment, it is difficult to follow what the magic numbers like `404` and `484` actually refer to.
https://review.coreboot.org/c/coreboot/+/83798/comment/7bfdc0b3_8195832e?usp... : PS50, Line 51: TDP_15W = 15 then you should have added other TDP macros as well ? as per my understanding we are actually starting with PTL-UH which is 25W.
https://review.coreboot.org/c/coreboot/+/83798/comment/4a718032_65a697ff?usp... : PS50, Line 60: PCI_DID_INTEL_PTL_U_ID_1 based on my understanding, we will also use `PCI_DID_INTEL_PTL_H_ID_1` for sometime (till next year) then in that case, we need to keep PCI_DID_INTEL_PTL_H_ID_1 and support configuration also enable (for 25W)
https://review.coreboot.org/c/coreboot/+/83798/comment/9349369e_61eb172f?usp... : PS50, Line 344: hybrid_storage_mode this is not applicable since MTL. please check
https://review.coreboot.org/c/coreboot/+/83798/comment/b35852dd_4ef0943b?usp... : PS50, Line 363: dmi_pwr_optimize_disable who is the consumer ? (I don't see anything during MTL). Also not sure if the DMI is still valid for PTL
File src/soc/intel/pantherlake/chip.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/b8d5ce1f_dc1a1e5c?usp... : PS50, Line 165: config don;t we need the NULL check ?
File src/soc/intel/pantherlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/798aa821_2eec33bd?usp... : PS50, Line 165: conf check for the NULL pointer