[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area

[Arthur Heymans (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email )

Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area
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Patch Set 4: Code-Review+1

(1 comment)

File src/soc/amd/common/block/include/amdblocks/iomap.h:

https://review.coreboot.org/c/coreboot/+/75611/comment/76e69bfd_3955eb19 :
PS4, Line 15: 0xfd00000000
That's typically where the full SPI flash is mapped too right (ROM3 register)?
Would it make sense to read that back from hardware rather than hardcoding it? I was told it's a setting in APCB.