[coreboot-gerrit] Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: V Sowmya, Martin Roth, Sugnan Prabhu S, Subrata Banik, Balaji Manigandan.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 )

Change subject: mb/intel/shadowmountain: Add bootblock and verstage code
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Patch Set 2:

(1 comment)

File src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/49479/comment/b81031eb_6a074949 
PS2, Line 35: 	*num = ARRAY_SIZE(early_gpio_table);
You'll want to add UART GPIOs here, we're pushing to have them set up here instead of in SoC code, see https://review.coreboot.org/q/topic:gpio_soc_to_boards